STABILITY ANALYSIS OF MTJ BASED SRAM BIT CELL USING 32NM TECHNOLOGY

Abstract

Avoiding data loss and maintaining data stability is one of the major parameters taken into consideration while dealing with the scaling of CMOS technology. Nevertheless, moving towards nano meter technology not only the nodes has increased, but also the variability in device properties has also enhanced due to large method variations. Static random-access memory (SRAM) is a conventional device that is used in advanced microprocessors because it requires less chip area, thereby making the device compact. It is mainly used for the storage of data for which read-write operations can be performed. The performance of the SRAM circuit can be analyzed by observing the data stability in read-write SNM (Static Noise Margin). The paper also includes the corresponding summary and simulation of both SRAM cells based on Read and Write operation. For performing a comparative study of performance parameters, in this paper we have performed a simulation-based study on CNTFET as well and then presented results in comparison with CMOS, Normally silicon technology is the choice for digital circuits but the properties of CNT such as high electron mobility, better carrier velocity and drive current than MOSFET, better control over threshold voltage make this technology provide better results in terms of static noise margin for both read and write operation. This paper also presents a brief idea about the simulation study performed on the 1T1MTJ MRAM cell based on the Spin Torque Transfer principle which is used for writing the data into the MRAM cell. Here for obtaining simulation results the MTJ used is of in-plane anisotropy with TMR (Tunnel magnetoresistance) of 1 (100%) which is one of the most fundamental and important spintronic phenomena for reading data. it is observed in the simulation results that the data that is written into the cell can be read through switching of the resistance which can be observed at the output node of the MRAM circuit. For all three technologies presented in this paper, we have used 32nm technology for simulation and for obtaining results the simulation tool used is Hspice with versions version A-2008.03 and version D-2010-SP1.