PERFORMANCE ANALYSIS OF HIGH SPEED SENSE AMPLIFIERS FOR LOW POWER APPLICATION WITH 45NM CMOS TECHNOLOGY

Authors

  • Thakurendra Singh, V. K. Tomar

Keywords:

Sense Amplifier, SRAM, CLSA, VLSA, FSPA, VLSA ALSA, LTSA

Abstract

This work introduces a novel sense amplifier to meet the demand for the most distinctive component of the memory. The proposed design is implemented in a memory cell, and the results are analysed to determine the memory chip degree. To overcome the latency of sensing techniques in memory systems, CPUs (central processing units), and high-end servers, a new sense amplifier (SA) is required. SRAM outperforms all other types of memory, including SRAM, DRAM, and non- volatile memories like ROM, PROM, and sense amplifiers. Using 45 nm CMOS technology, a 6T SRAM cell with a unique sense amplifier has been built. Modified sense amplifier circuits such as linked, clamped bit line, latch type, and hybrid type have been implemented. The sensing latency of various kinds of sense amplifiers is analysed with C bit line and power delivery variations in mind. On the basis of area, power, and delay, the design of a sense amplifier was evaluated. The proposed design's major goal is to boost the speed of SRAM to introduce sense amplifier. Static Random Access memory based on VLSA,  FSPA-VLSA, CLSA,  ALSA, and LTSA topologies has designed and functionality is verified with 45nm  CMOS deep nano-meter technology. By decreasing the sensing electricity inside the Sense amplifier, the interval and power dissipation of the recollection's overall performance influence, and later the ultimate performance of the remembrance increase

Published

2021-12-26

How to Cite

Thakurendra Singh, V. K. Tomar. (2021). PERFORMANCE ANALYSIS OF HIGH SPEED SENSE AMPLIFIERS FOR LOW POWER APPLICATION WITH 45NM CMOS TECHNOLOGY. Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology, 53(12), 197–203. Retrieved from http://hebgydxxb.periodicales.com/index.php/JHIT/article/view/783

Issue

Section

Articles