GLOBALLY-ASYNCHRONOUS LOCALLY-SYNCHRONOUS NETWORK-ON-CHIP (GALS-NoC) ARCHITECTURE FOR FPGAs

Abstract

Point-to-point or shared-bus interconnects alone cannot meet the demands of scalable, low latency, and power-efficient System-On-Chip interconnect. In this research, we suggest a novel low-latency asynchronous Network-On-Chip (NOC) architecture. In order to implement this architecture, a GALS system is used, in which chip units are constructed as synchronous islands and coupled via a Delay Insensitive asynchronous Network-on-Chip topology. The proposed NOC protocol, its asynchronous implementation, and a multi-level modeling strategy based on the System C language and Transaction-Level Modeling are all given. According to preliminary simulation results, the Asynchronous NOC can provide throughput of 5 Gbytes/s. The GALS scheme will be presented as an intermediate design approach with current results in asynchronous Network-on-Chip for future Many Core designs, as well as the principles and benefits of asynchronous logic and some thoughts on upcoming research problems. Recent asynchronous logic applications in the microelectronics sector will be described in terms of industrial acceptability, with a primary focus on the current commercial CAD tools.